Senior Design Verification Engineer - Mixed Signal | Austin, Texas
For an exciting, well-funded startup developing leading-edge technology for next-generation high-speed communications, we are seeking a Mixed-Signal Verification Engineer to join our team.
Key Responsibilities
- Develop verification strategies for digital and analog (mixed-signal) designs using UVM methodologies based on design specifications.
- Create behavioral models for analog blocks in accordance with guidelines provided by analog designers.
- Write, execute, and debug UVM-based testbenches using SystemVerilog for mixed-signal blocks.
- Run and debug behavioral model validation using AMS tools to ensure model correctness.
- Perform and troubleshoot unit-level, cluster-level, and top-level simulations of mixed-signal designs.
Minimum Qualifications
- 5 or more years of relevant experience.
- Experience in behavioral modeling of analog designs for digital verification.
- Knowledge of mixed-signal dynamic verification using digital design tools without AMS.
- Proficiency in Verilog and SystemVerilog coding.
- Experience with Virtuoso schematic tools.
- Basic knowledge of analog design principles.
Preferred Qualifications
- Experience with UVM methodologies.
- Experience with both Synopsys and Cadence tools.
Additional Skills
- Verification Methodologies and Tools: Familiarity with verification methodologies and tools such as simulators, waveform viewers, execution automation, and coverage collection. Proven ability to develop scalable and portable test cases.
- Collaborative Environment: Ability to verify analog and mixed-signal designs in a collaborative team environment.
- Communication: Strong communication skills, including writing test plans, presenting results, and working effectively with cross-functional teams.
