An innovative and well-funded technology start-up developing next-generation high-speed communication solutions is seeking a Senior Verification Engineer to spearhead its growing engineering team. This role focuses on driving complex RTL design verification across multiple design components and contributing to the development of cutting-edge communication technology.
You will play a key role in defining and implementing verification strategies, building robust verification environments, and ensuring design quality across sophisticated digital systems. This is an opportunity to work closely with multidisciplinary teams including architecture, algorithm, and design engineers in a highly collaborative environment.
What you’ll be doing:
- Get hands-on owning block/cluster verification end-to-end from planning to closure.
- Define verification plans, testbench architecture, and functional coverage.
- Develop verification environments using SystemVerilog and UVM.
- Work closely with design, architecture, and algorithm teams to debug and validate functionality.
- Track coverage metrics and drive verification closure.
- Support and mentor less experienced engineers.
What you need:
- 10+ years of verification experience.
- Completed 2+ full block/system verification cycles.
- Strong familiarity and practical experience with UVM or eRM
- Experience with data path or communication protocols; Ethernet is a plus.
What’s in it for you?
- Work at the sharp end of next-generation high-speed communication technology.
- Join a well-funded, fast-growing start-up with significant technical challenges.
- High level of ownership and influence on architecture and verification strategy.
- Collaborative team environment with opportunities to mentor and shape engineering practices from the outset.
If you are an accomplished and experienced verification engineer looking to take the next step at the forefront of tomorrow's technology, apply today!
