The Oho Group have partnered with an exciting GPU startup in the AI space looking for a Senior SoC Designer to lead frontend RTL design for next-generation AI acceleration systems.
Responsibilities
- Develop and optimize RTL for AI centric hardware subsystems
- Implement micro-architectures focused on datapaths, memory, and performance
- Drive PPA optimization across frequency, power, and area targets
- Lead synthesis, timing closure, and frontend verification
- Collaborate with architecture teams on HW/SW co-optimization for AI workloads
Requirements
- 5+ years in silicon/ASIC frontend design
- Strong RTL expertise in Verilog/SystemVerilog
- Experience with synthesis, timing analysis, verification, and power optimization
- Deep understanding of PPA trade-offs and memory bandwidth optimization (SRAM)
- Proficiency with EDA tools including Verilator, Yosys, and OpenSTA
Preferred
- AI accelerator or NPU design experience
- ML-for-EDA or AI-assisted hardware optimization background
- Edge AI or automotive safety familiarity
