Lead Physical Design Engineer
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Lead Physical Design Engineer

Reference: zblpd
Location
San Francisco, CA, USA
Salary
$250,000 - $300,000
Contract Type
Permanent
Work Arrangement
Hybrid
Skill Requirements
  • ASIC Design Engineer

Lead Physical Design Engineer - Well-Backed Startup - San Francisco Bay Area

 

About the Role

The Oho Group have partnered with a very well-backed Startup in the Bay Area looking for an experienced Physical Design Engineer to lead the implementation of complex ASIC and SoC designs from floorplanning through to tape-out. This is a senior technical leadership role, combining hands-on physical design expertise with responsibility for methodology, technical direction, and mentoring a high-performing engineering team.

 

Key Responsibilities

  • Lead full-chip and subsystem physical design, taking designs from netlist through implementation and signoff.
  • Own floorplanning, power planning, placement, clock tree synthesis (CTS), routing, timing closure and physical verification.
  • Develop and improve physical design methodologies, flows and automation.
  • Lead timing closure activities and collaborate closely with STA engineers to resolve critical timing issues.
  • Work closely with RTL, synthesis, DFT, packaging and architecture teams throughout the development cycle.
  • Mentor and support Physical Design engineers while providing technical leadership across projects.

 

Requirements

  • Degree in Electrical Engineering, Electronics, Computer Engineering or a related discipline.
  • Strong expertise across the complete physical design flow using industry-standard implementation tools.
  • Experience delivering advanced-node designs
  • Deep understanding of floorplanning, CTS, routing, timing closure, signal integrity and physical verification.
  • Experience with power integrity analysis, including IR drop and electromigration.

 

Desirable Experience

  • High-speed interface or PHY implementation (DDR, LPDDR, HBM or similar).
  • Mixed-signal or analog IP integration.
  • Advanced packaging, chiplet or 3D-IC technologies.
  • IP hardening and external IP delivery.
  • Experience working on high-volume production silicon.

 

If you're looking to take real responsibility and lead development of advanced AI technology, then this is the role for you! Make sure to apply today as interviews are already being scheduled.

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Zak Bowyer
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