ASIC Design Engineer – Austin – AI Accelerator Startup
Key Responsibilities
- Own RTL design and microarchitecture.
- Work on cache-coherent and non-coherent interconnects and associated protocols.
- Define and review microarchitectural specifications and translate them into robust, synthesizable RTL.
- Work closely with verification engineers on design validation, debugging and performance analysis.
- Collaborate with architecture, verification, software and system teams throughout the silicon development cycle.
What We're Looking For
- 10+ years of ASIC/SoC design experience, with substantial hands-on RTL development.
- Strong Verilog/SystemVerilog RTL design experience.
- Experience designing complex SoCs, NoCs, interconnects, fabrics or high-performance processors.
- Familiarity with technologies such as PCIe, CXL or UCIe.
- Experience working on GPUs, AI accelerators, CPUs, TPUs is highly desirable.
- Experience with HBM, memory controllers or coherent fabrics is a strong plus.
Education
BS, MS or PhD in Electrical Engineering, Computer Engineering, Computer Science or a related field.
